High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture

ABSTRACT

The invention encompasses several improved Turbo codes method to provide a more practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP coding. (1) Two pipelined Log-MAP decoders are used for iterative decoding of received data. (2) Output data from the first decoder A are stored in the Interleaver RAM memory, and the second decoder B stores output data in the De-interleaver RAM memory, such that in pipeline mode Decoder A decodes data from the De-interleaver RAM memory while the Decoder B decodes data from the De-interleaver RAM memory at the same time. (3) Log-MAP decoders are simpler to implement in ASIC with only Adder circuits, and are low-power consumption. (4) Pipelined Log-MAP decoders method provide high speed data throughput.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] Referenced-Applications

[0002] This patent is based upon the development of IP Core ASICproducts for 3G-WDMA and 3G-CDMA2000 wireless communicationsapplications by IComm Technologies, Inc. since early 1998. Other U.S.Patent References: U.S. Pat. No. 6,023,783 February 2000 Divsalar et al.U.S. Pat. No. 5,233,629 August 1993 Paik et al. U.S. Pat. No. 5,446,747August 1995 Berrou U.S. Pat. No. 5,721,745 February 1998 Hladik et al.U.S. Pat. No. 5,729,560 March 1998 Hagenauer et al. U.S. Pat. No.5,734,962 March 1998 Hladik et al.

BACKGROUND OF INVENTION

[0003] 1. Field of the Invention

[0004] This invention relates to Baseband Processor and Error-CorrectionCodes for 3G Wireless Mobile Communications; and more particularly, to avery high speed Turbo Codes Decoder using pipelined Log-MAP decodersmethod for 3G CDMA2000 and 3G WCDMA.

[0005] 2. Description of Prior Art

[0006] A Turbo Codes Decoder is an important baseband processor of thedigital wireless communication Receiver, which was used to reconstructthe corrupted and noisy received data and to improve BER(bit-error-rate) throughput. The FIG. 1 shows an example of a 3GReceiver with a Turbo Codes Decoder 13 which decodes data from theDemodulator 11 and De-mapping 12 modules, and sends decoded data to theMAC layer 14. The FIG. 2 shows an example of an 8-PSK constellationpoints 21 produced by the Demodulator module 11. The De-mapping 12module uses the 8-PSK constellation points 21 to convert into binarydata 22 and send to the Turbo Codes Decoder 13. The data 22 is thendecoded and reconstructed by the Turbo Codes Decoder 13 and send to theMAC layer 14.

[0007] A most widely used FEC is the Viterbi Algorithm Decoder in bothwired and wireless application. The drawback is that it would requires along waiting for decisions until the whole sequence has been received. Adelay of six time the memory of the received data is required fordecoding. One of the more effective FEC, with higher complexity, a MAPalgorithm used to decode received message has comprised the steps ofvery computational complex, requiring many multiplications and additionsper bit to compute the posteriori probability. The major difficulty withthe use of MAP algorithm has been the implementation in semiconductorASIC devices, the complexity the multiplications and additions whichwill slow down the decoding process and reducing the throughput datarates. Furthermore, even under the best conditions, each multiplicationwill be used in the MAP algorithm, that would create a large circuits inthe ASIC. The result is costly, and low performance in bit ratesthroughput.

[0008] Recently introduced by the 3GPP organization a new class of codesusing parallel concatenated codes as shown in FIG. 3 similar to thereference and patents to Berrou describing a basic parallel concatenatedcodes which is known as Turbo Codes. An example of the Turbo Codes with8-states and rate 1/3 is shown in FIG. 3, data enters the two systematicencoders 31 33 separated by an interleaver 32. An output codewordconsists of the source data bit followed by the parity check bits of thetwo encoders. Another U.S. Pat. No. 6,023,783 by Divsalar and Pollaradescribes a more improved encoding method than Berrou and some basicmathematical concepts of parallel concatenated codes. However, patentsby Berrou, the U.S. Pat. No. 6,023,783, and others only describe thebasic concept of parallel concatenated codes using mathematicalequations which are good for research in deep space communications andother government projects but are not feasible, economical, andpractical for consumers. The encoding of data is simple and can beeasily implemented with a few xor and flip-flop logic gates. But thedecoding the Turbo Codes is much more difficult to implement in ASIC orsoftware. The prior arts describe briefly the implementation of theTurbo Codes Decoder which are mostly for deep space communications andrequires much more hardware, powers and costs.

[0009] All the prior arts of Turbo Codes fail to achieve a simplermethod for a Turbo Codes Decoder as it is required and desired for 3Gcellular phones and 3G personal communication devices including highspeed data throughput, low power consumption, lower costs, limitedbandwidth, and limited power transmitter in noisy environment.

SUMMARY OF INVENTION

[0010] The present invention concentrates only on the Turbo CodesDecoder to implement a more efficient, practical and simpler method toachieve the requirements for 3G cellular phones and 3G personalcommunication devices including higher speed data throughput, lowerpower consumptions, lower costs, and simpler implementation in ASIC orsoftware. The present invention encompasses improved and simplifiedTurbo Codes Decoder method and apparatus to deliver higher speed andlower power especially for 3G applications. Our Turbo Codes Decoderutilizes two pipelined and serially concatenated SISO Log-MAP Decoderswith Interleaver-Memory at the output of the first decoder and aDe-interleaver-Memory at the second decoder. The two decoders functionin a pipelined scheme; while the first decoder is decoding data in thede-interleaver-Memory, the second decoder performs decoding data in theinterleaver-Memory, which produces a decoded output every clock cycle inresults. Accordingly, several objects and advantages of our Turbo CodesDecoder are:

[0011] To deliver higher speed throughput and lower power consumption

[0012] To utilize SISO Log-MAP decoder for faster decoding andsimplified implementation in ASICr with the use oformary adders forcomputation.

[0013] To perform re-iterative decoding of data back-and-forth betweenthe two Log-MAP decoders in a pipelined scheme until a decision is made.In such pipelined scheme, a decoded output data is produced each clockcycle.

[0014] To improve higher performance in term of symbol error probabilityand low BER for 3G applications such as 3G W-CDMA, and 3G CDMA2000operating at very high bit-rate up to 100 Mbps in a low power noisyenvironment.

[0015] To utilize an simplified and improved architecture of SISOLog-MAP decoder including branch-meric (BM) calculations module,recursive state-metric (SM) forward/backward calculations module,Log-MAP posteriori probability calculations module, and output decisionmodule.

[0016] To reduce complexity of multiplier circuits in MAP algorithm byperform the entire MAP algorithm in Log domain with the uses of binaryder circuits which are more suitable for ASIC implementation while stillmaintain a high level of performance output.

[0017] To design an improve Log-MAP Decoder using high level designlanguage of VHDL which can be synthesized into custom ASIC and FPGAdevices.

[0018] Still further objects and advantages will become apparent to oneskill in the art from a consideration of the ensuing descriptions andaccompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0019]FIG. 1 is a typical 3G Receiver Functional Block Diagram which useTurbo Codes Decoder for error-correction.

[0020]FIG. 2 is an example of an 8-PSK (QPSK) constellations of thereceiving signals.

[0021]FIG. 3 is a block diagram of the 8-states Parallel ConcatenatedConvolutional Codes.

[0022]FIG. 4 is the Turbo Codes Decoder System Block Diagram showingLog-MAP Decoder, Interleavers, Input Shift registers and control logics.

[0023]FIG. 5 is a block diagram of the Input Buffer Shift Registers.

[0024]FIG. 5b is the Soft Values Mapping ROM Table.

[0025]FIG. 6 is the input Buffer Interface Timing.

[0026]FIG. 7 is a block diagram of the 8-states SISO Log-MAP Decodershowing Branch Metric module, State Metric module, Log-MAP module, amState and Branch Memory modules.

[0027]FIG. 8 is the 8-States Trellis Diagram of a SISO Log-MAP Decoder.

[0028]FIG. 9 is a block diagram of the BRANCH METRIC COMPUTING module.

[0029]FIG. 10a is a block diagram of the Log-MAP computing for u=0.

[0030]FIG. 10b is a block diagram of the Log-MAP computing for u=1.

[0031]FIG. 11 is a block diagram of the Log-MAP Compare & Select Imaximumogic for each state.

[0032]FIG. 12 is a block diagram of the Soft Decode module.

[0033]FIG. 13 is a block diagram of the Computation of Forward Recursionof stSte-m Mric module (FACS).

[0034]FIG. 14 is a block diagram of the Computation of BackwardRecursion of st Ste-m Mric module (BACS).

[0035]FIG. 15 showing FoState Metric rward computing of Trellis statetransitions.

[0036]FIG. 16 showing BaState Metric ckward computing of Trellis statetransitions.

[0037]FIG. 17 is a block diagram of the State Machine operations ofLog-MAP Decoder.

[0038]FIG. 18 is a block diagram of the BM dual-port Memory Module.

[0039]FIG. 19 is a block diagram of the SM dual-port Memory Module.

[0040]FIG. 20 is a block diagram of the Interleaver RAM Memory MemoryModule.

[0041]FIG. 21 is a block diagram of the De-Interleaver RAM MemoryModule.

[0042]FIG. 22 is a block diagram of the State Machine operations of theTurbo Codes Decoder.

[0043]FIG. 23 is a block diagram of the Iterative decoding feedbackcontrol Mux.

DETAILED DESCRIPTION

[0044] Turbo Codes Decoder

[0045] As shown in FIG. 4, a Turbo Codes Decoder has two concatenatedLoSISO g-MAP Decoders A 42 and B 44 connected in a feedback loop withInterleaver Memory 43 and De-Interleaver Memory 45 in between. An inputBuffer 41, shown in details FIG. 5, has one serial-to-par (S/P)converter 51, and three shift registers 52 of length N for blockdecoding. A control logic module (CLSM) 47, shown in FIG. 4, consists ofvarious state-machines which in turn control all the operations of theTurbo Codes Decoder. The hard-decoder module 46 outputs the finaldecoded data. Signals R2, R1, R0 are the received data shifted out fromthe Shift Registers. Signal XO1, and XO2 are the output soft decision ofthe Log-MAP Decoders A 42 and B 44 respectively, which are stored in theInterleaver Memory 43 and De-Interleaver Memory 45 module. Signal Z2 andZ1 are the output of the Interleaver Memory 43 and De-Interleaver Memory45 where the Z2 is feed into Log-MAP decoder B 44, and Z1 is feedbackinto Log-MAP decoder A 42 for iterative decoding.

[0046] In accordance with the invention, the Turbo Codes Decoder decodesan 8-state Parallel Concatenated Convolutional Code (PCCC), with codingrate 1/3, constraint length K=4, using L SISOog-MAP (Maximum aPosteriori) Decoders in pipeline. The Turbo Codes Decoder can alsodecode a 16-states or more PCCC with different code rates.

[0047] As shown in FIG. 1 the Turbo Codes Decoder functions effectivelyas follows:

[0048] Serial received data are shifted into 3 Shift Registers toproduce R0, R1, and R2 data sequence.

[0049] The soft value module converts the input data R0, R1, and R2 into3-bit quantization soft-values according to TABLE 1.

[0050] When a block of N input data is received, the Turbo Decoderstarts the Log-MAP Decoder A to decode the N input bits based on thesoft-values of R0 and R1, then stores the outputs in the InterleaverMemory.

[0051] Next, the Turbo Decoder starts the Log-MAP Decoder B to decodethe N input bits based on the soft-values of R2 and Z2, then store theoutputs in the De-Interleaver Memory.

[0052] The Turbo Decoder will now do the iterative decoding for L numberof times. The Log-MAP Decoder A now uses the signals Z1 and R1 asinputs. The Log-MAP Decoder B uses the sigZ2 and R2 as inputs.

[0053] When the iterative decoding sequences are done, the Turbo Decoderstarts the hard-decision operations to compute and produce soft-decisionoutputs.

[0054] Input Buffer Shift Registers

[0055] As shown in FIG. 5, the Turbo Codes Input Buffer has aserial-to-parallel (S/P) converter 51, and three Shift Registers 52 of Nbits to store each block of N input data. A 3-bit Serial-to Parallel(S/P) converter 51 converts input data into 3 serial data streams whichare then shifted into the corresponding shift registers 52. As shown inFIG. 6 is the timing interface with the input buffer from the externalhosts or the Demodulator/De-mapping 12. A bit clock (BCLK) inconjunction with the frame sync (RSYNC) are used to shift data into theS/P converter 51 when the RSYNC is active (HIGH).

[0056] As shown in FIG. 5b, each input data bit R0, R1, and R2 enteringinto the Log-MAP Decoder are assigned a soft-value of L-bit quantizationas shown in the following TABLE 1. The same soft values are used as thethreshold for the final hard code data. TABLE 1 Soft values Soft ValuesL-bit Input data Bit . . . 011 0 . . . 101 1

[0057] SISO Log-MAP Decoder

[0058] As shown in FIG. 7, an SISO Log-MAP Decoder 42 44 comprises of aBranch Metric (BM) computation module 71, a State Metric (SM)computation module 72, a Log-MAP computation module 73, a BM Memorymodule 74, a SM Memory module 75, and a Control Logic State Machinemodule 76. Soft-values inputs enter the Branch Metric (BM) computationmodule 71, where Euclidean distance is calculated for each branch, theoutput branch metrics are stored in the BM Memory module 74. The StateMetric (SM) computation module 72 reads branch metrics from the BMMemory 74 and compute the state metric for each state, the outputstate-metrics are stored in the SM Memory module 75. The Log-MAPcomputation module 73 reads both branch-metrics and state-metrics fromBM memory 74 and SM memory 75 modules to compute the Log Maximum aPosteriori probability and produce soft-decision output. The ControlLogic State-machine module 76 provides the overall operations of thedecoding process.

[0059] As shown in FIG. 7, the Log-MAP Decoder 42 44 functionseffectively as follows:

[0060] The Log-MAP Decoder 42 44 reads each soft-values (SD) data pairinput, then computes branch-metric (BM) values for all 16 paths in theTurbo Codes Trellis 85 as shown in FIG. 8, then stores all 16 BM datainto BM Memory 74. It repeats computing BM values for each input datauntil all N samples are calculated and stored in BM Memory 74.

[0061] The Log-MAP Decoder 42 44 reads BM values from BM Memory 74 andSM values from SM Memory 75, and computes the forward state-metric (SM)for all 8 states in the Trellis 85 as shown in FIG. 8, then store all 8forward SM data into SM Memory 75. It repeats computing forward SMvalues for each input data until all N samples are calculated and storedin SM Memory 75.

[0062] The Log-MAP Decoder 42 44 reads BM values from BM Memory 74 andSM values from SM Memory 75, and computes the backward state-metric (SM)for all 8 states in the Trellis 85 as shown in FIG. 8, then store all 8backward SM data into the SM Memory 75. It repeats computing backward SMvalues for each input data until all N samples are calculated and storedin SM Memory 75.

[0063] The Log-MAP Decoder 42 44 then computed Log-MAP posterioriprobability for u=0 and u=1 using BM values and SM values from BM Memory74 and SM Memory 75. It repeats computing Log-MAP posteriori probabilityfor each input data until all N samples are calculated. The Log-MAPDecoder then decodes data by making soft decision based on theposteriori probability for each stage and produce soft-decision output,until all N inputs are decoded.

[0064] Branch Metric Computation module

[0065] The Branch Metric (BM) computation module 71 computes theEuclidean distance for each branch in the 8-states Trellis 85 as shownin the FIG. 8 based on the following equations:

Local Euclidean distances values SD0*G0+SD1*G1

The SD0 and SD1 are soft-values from TABLE 1, G0 and G1 are the expectedinput for each path in the Trellis 85. G0 and G1 are coded as signedantipodal values, meaning that 0 corresponds to +1 and 1 corresponds to−1. Therefore, the local Euclidean distances for each path in theTrellis 85 are computed by the following equations:

M1=SD0+SD1

M2=−M1

M3=M2

M4=M1

M5=−SD0+SD1

M6=−M5

M7=M6

M8=M5

M9=M6

M10=M5

M11=M5

M12=M6

M13 M2

M14=M1

M15=M1

M16=M2

[0066] As shown in FIG. 9, the Branch Metric Computing module compriseof one L-bit Adder 91, one L-bit Subtracter 92, and a 2′complemeter 93.It computes the Euclidean distances for path M1 and M5. Path M2 is2′complement of path M1. Path M6 is 2′complement of M5. Path M3 is thesame path M2, path M4 is the same as path M1, path M7 is the same aspath M6, path M8 is the same as path MS, path M9 is the same as path M6,path M10 is the same as path MS, path M11 is the same as path MS, pathM12 is the same as path M6, path M13 is the same as path M2, path M14 isthe same as path M1, path M15 is the same as path M1, and path M16 isthe same as path M2.

[0067] State Metric Computing module

[0068] The State Metric Computing module 72 calculates the probabilityA(k) of each state transition in forward recursion and the probabilityB(k) in backward recursion. FIG. 13 shows the implementation ofstate-metric in forward recursion with Add-Compare-Select (ACS) logic,and FIG. 14 shows the implementation of state-metric in backwardrecursion with Add-Compare-Select (ACS) logic. The calculations areperformed at each node in the Turbo Codes Trellis 85 (FIG. 8) in bothforward and backward recursion. The FIG. 15 shows the forward statetransitions in the Turbo Codes Trellis 85 (FIG. 8), and FIG. 16 show thebackward state transitions in the Turbo Codes Trellis 85 (FIG. 8). Eachnode in the Trellis 85 as shown in FIG. 8 has two entering paths:one-path 84 and zero-path 83 from the two nodes in the previous stage.

[0069] The ACS logic comprises of an Adder 132, an Adder 134, aComparator 131, and a Multiplexer 133. In the forward recursion, theAdder 132 computes the sum of the branch metric and state metric in theone-path 84 from the state s(k−1) of previous stage (k−1). The Adder 134computes the sum of the branch metric and state metric in the zero-path83 from the state (k−1) of previous stage (k−1). The Comparator 131compares the two sums and the Mulitplexer 133 selects the larger sum forthe state s(k) of current stage (k). In the backward recursion, theAdder 142 computes the sum of the branch metric and state metric in theone-path 84 from the state s(j+1) of previous stage (J+1). The Adder 144computes the sum of the branch metric and state metric in the zero-path83 from the state s(j+1) of previous stage (J+1). The Comparator 141compares the two sums and the Mulitplexer 143 selects the larger sum forthe state s(j) of current stage (j).

[0070] The Equations for the ACS are shown below:

A(k)=MAX[(bm0+sm0(k−1)), (bm1+sm1(k−1)]

B(j)=MAX[(bm0+sm0(j+1)), (bm1+sm1(j+1)]

[0071] Time (k−1) is the previous stage of (k) in forward recursion asshown in FIG. 15, and time (j+1) is the previous stage of (j) inbackward recursion as shown in FIG. 16.

[0072] Log-MAP Computing Module

[0073] The Log-MAP computing module calculates the posterioriprobability for u=0 and u=1, for each path entering each state in theTurbo Codes Trellis 85 corresponding to u=0 and u=1 or referred aszero-path 83 and one-path 84. The accumulated probabilities are comparedand selected the u with larger probability. The soft-decision are madebased on the final probability selected for each bit. FIG. 10a shows theimplementation for calculating the posteriori probability for u=0. FIG.10b shows the implementation for calculate the posteriori probabilityfor u=1. FIG. 11 shows the implementation of compare-and-select the uwith larger probability. FIG. 12 shows the implementation of thesoft-decode compare logic to produce output bits based on the posterioriprobability of u=0 and u=1. The equations for calculation theaccumulated probabilities for each state and compare-and-select areshown below:

sum _(—) s00=sm0i30 bm1+sm0j

sum _(—) s01=sm3i+bm7+sm1j

sum _(—) s02=sm4i+bm9+sm2j

sum _(—) s03=sm7i+bm15+sm3j

sum _(—) s04=sm1i+bm4+sm4j

sum _(—) s05=sm2i+bm6+sm5j

sum _(—) s06=sm5i+bm12+sm6j

sum _(—) s07=sm6i+bm14+sm7j

sum _(—) s10=sm1i+bm3+sm0j

sum _(—) s11=sm2i+bm5+sm1j

sum _(—) s12=sm5i+bm1+sm2j

sum _(—) s03=sm6i+bm13+sm3j

sum _(—) s14=sm0i+bm2+sm4j

sum _(—) s15=sm3i+bm8+sm5j

sum _(—) s16=sm4i+bm10+sm6j

sum _(—) s17=sm7i+bm16+sm7j

s00sum=MAX[sum _(—) s00, 0]

s01sum=MAX[sum _(—) s01, s00sum]

s02sum=MAX[sum _(—) s02, s01sum]

s03sum=MAX[sum _(—) s03, s02sum]

s04sum=MAX[sum _(—) s04, s03sum]

s05sum=MAX[sum _(—) s05, s04sum]

s06sum=MAX[sum _(—) s06, s05sum]

s07sum=MAX[sum _(—) s07, s06sum]

s10sum=MAX[sum _(—) s10, 0]

s11sum=MAX[sum _(—) s11, s10sum]

s12sum=MAX[sum _(—) s12, s11sum]

s13sum=MAX[sum _(—) s13, s12sum]

s14sum=MAX[sum _(—) s14, s13sum]

s15sum=MAX[sum _(—) s15, s14sum]

s16sum=MAX[sum _(—) s16, s15sum]

s17sum=MAX[sum _(—) s17, s16sum]

[0074] Control Logics—State Machine (CLSM) Module

[0075] As shown in FIG. 7 the Control Logics module controls the overalloperations of the Log-MAP Decoder. The control logic state machine 171,referred as CLSM, is shown in FIG. 17. The CLSM module 171 (FIG. 17)operates effectively as the followings. Initially, it stays in IDLEstate 172. When the decoder is enable, the CLSM transitions to CALC-BMstate 173, it then starts the Branch Metric (BM) module operations andmonitor for completion. When Branch Metric calculations are done,referred as bm-done the CLSM transitions to CALC-FWD-SM state 174, itthen tarts the State Metric module (SM) in forward recursion operation.When the forward SM state metric calculations are done, referred asfwd-sm, the CLSM transitions to CALC-BWD-SM state 175, it then startsthe State Metric module (SM) in backward recursion operations. Whenbackward SM state metric calculations are done, referred as bwd-sm-donethe CLSM transitions to CALC-Log-MAP state 176, it then starts theLog-MAP computation module to calculate the maximum a posterioriprobability to produce soft decode output. When Log-MAP calculations aredone, referred as log-map-done, it transitions back to IDLE state 172.

[0076] BM Memory and SM Memory

[0077] The Branch-Metric Memory 74 and the State-Metric Memory 75 areshown in FIG. 7 as the data storage components for BM module 71 and SMmodule 72. The Branch Metric Memory module is a dual-port RAM containsM-bit of N memory locations as shown in FIG. 18. The State Metric Memorymodule is a dual-port RAM contains K-bit of N memory locations as shownin FIG. 19. Data can be written into one port while reading at the otherport.

[0078] Interleaver Memory and De-Interleaver Memory

[0079] As shown in FIG. 4, the Interleaver Memory 43 stores data for thefirst decoder A 42, and De-interleaver memory 45 stores data for thesecond decoder B 44. In an iterative pipelined decoding, the decoder A42 reads data from De-interleaver memory 45 and writes results data intoInterleaver memory 43, the decoder B 44 reads data from Interleavermemory 43 and write results into De-interleaver memory 45.

[0080] As shown in FIG. 20, the Interleaver memory 43 comprises of anInterleaver module 201 and a dual-port RAM 202 contains M-bit of Nmemory locations. The Interleaver is a Turbo code internal interleaveras defined by 3GPP standard ETSI TS 125 222 V3.2.1 (2000-05). TheInterleaver permutes the address input port A for all write operationsinto dual-port RAM module. Reading data from output port B are done withnormal address input.

[0081] As shown in FIG. 21, the De-Interleaver memory 45 comprises of anDe-interleaver module 211 and a dual-port RAM 212 contains M-bit of Nmemory locations. The De-Interleaver is a Turbo code internalinterleaver as defined by 3GPP standard ETSI TS 125 222 V3.2.1(2000-05). The De-Interleaver permutes the address input port A for allwrite operations into dual-port RAM module. Reading data from outputport B are done with normal address input.

[0082] Turbo Codes Decoder Control Logics—State Machine (TDCLSM)

[0083] As shown in FIG. 4 the Turbo Decoder Control Logics module 47,referred as TDCLSM, controls the overall operations of the Turbo CodesDecoder. The state-machine is shown in the FIG. 22. Initially, theTDCLSM 47 stays in IDLE state 221. When decoder enable signal is active,the TDCLSM 47 transitions to INPUT states 222. The TDCLSM 47 starts theinput shifting operations until the input buffer 41 is full indicated byinput-ready signal. Then, the TDCLSM 47 transitions to Log-MAP A state223 and starts the operations of the Log-MAP Decoder A 42. When theLog-MAP A 42 is done, the TDCLSM 47 transitions to the Log-MAP B state224 and starts the Log-MAP Decoder B 44. When Log-MAP B 44 is done, theTDCLSM 47 starts the iterative decoding for J number of times. When theiterative decoding sequences are done, the TDCLSM 47 transitions toHARD-DEC state 225 and produces the hard-decode outputs. Then the TDCLSM47 transitions to the INPUT state to start decoding another block ofdata.

[0084] Iterative Decoding

[0085] Turbo Codes decoder performs iterative decoding L times byfeeding back the output Z1 of the second Log-MAP decoder B into thefirst Log-MAP decoder A, before making decision for hard-decodingoutput. As shown in FIG. 13, the Counter 233 count the preset number Ltimes, the Multiplexer select the input for the Decoder A. When Counteris zero, the Mux selects the input R1, else it selects the recursiveinput Z1 from Decoder B.

1. A turbo codes decoder used as a baseband processor subsystem foriterative decoding a plurality of sequences of received data R_(n)representative of coded data X_(n) generated by a turbo codes encoderfrom a source of original data u_(n) into decoded data x_(n) comprisingof: (a) two pipelined SISO Log-MAP Decoders each decoding input datafrom the other output data in an iterative mode; (b) the first SISOLog-MAP Decoder having three inputs: R₀, R₁ connecting from the Inputshift register module, and Z₁ feeding-back from the De-InterleaverMemory module output; and the first Decoder output is connected to anInterleaver Memory module; (c) the second SISO Log-MAP Decoder havingtwo inputs: R₂ connecting from the Input shift register module, and Z₂connecting from the Interleaver Memory module output; and the secondDecoder output is connected to a De-Interleaver RAM; (d) an InterleaverMemory module storing decoded data from the first Log-MAP Decoder,feeding data to the second Log-MA Decoder; (e) a De-Interleaver Memorymodule storing decoded data from the second Log-MAP Decoder,feeding-back data to the first Log-MAP Decoder; (f) an Input ShiftRegister Buffer storing a block input un-decoded received data, andfeeding data to the two Log-MAP Decoders; (g) a Control logic statemachine controlling the overall operations of the Turbo Codes Decoder;(h) a hard-decoder logic producing a final decision of either logic zero0 or logic one 1 at the end of the iterations.
 2. The Decoder system ofclaim c1, wherein each Log-MAP decoder uses the logarithm maximum aposteriori probability algorithm.
 3. The Decoder system of claim c1,wherein each Log-MAP decoder uses the soft-input and soft-output (SISO)logarithm maximum a posteriori probability algorithm.
 4. The Decodersystem of claim c1, wherein the Interleaver Memory module uses apermuter to generate the write-address sequences of the Memory core inwrite-mode. In read-mode, the memory core read-address are normalsequences.
 5. The Decoder system of claim c1, wherein the InterleaverMemory module uses dual-port memory RAM.
 6. The Decoder system of claimc1, wherein the De-Interleaver Memory module uses an inverse-permuter togenerate the write-address sequences of the Memory core in write-mode.In read-mode, the memory core read-address are normal sequences.
 7. TheDecoder system of claim c1, wherein the De-Interleaver Memory moduleuses dual-port memory RAM.
 8. A method for iterative decoding aplurality of sequences of received data R_(n) representative of codeddata X_(n) generated by a Turbo Codes Encoder from a source of originaldata u_(n) into decoded data x_(n) comprising the steps of: (a) couplingtwo pipelined decoders, having Interleaver Memory and De-InterleaverMemory for storing decoded output and providing feedback input for thedecoders; (b) applying feedback signal from the output of theDe-Interleaver Memory to the first decoder with the received signalinput to generate a first decoded output; (c) applying the first decodedoutput to the Interleaver Memory using the permuter to generate a memoryaddress for storing the decoded data; (d) applying the output of theInterleaver Memory to the second decoder with the received signal inputto generate a second decoded output applying the second decoded outputto the De-Interleaver Memory using the inverse-permuter to generate amemory address for storing the decoded data
 9. An 8-state SISO Log-MAPDecoder for decoding a plurality of sequences of soft-input data SD₀ andSD₁ generated by a receiver to produce decoded soft-output data Ycomprising of: (a) a Branch Metric module computing the two soft-inputdata SD₀ and SD into 16 branch metric values for each branch in thetrellis; (b) a Branch Metric Memory module storing the 16 branch metricvalues for each stage k=0 . . . N; (c) a State Metric module computingstate metric values for each state in the trellis using branch metricvalues; (d) a State Metric Memory module storing 8 state metric valuesfor each stage k=0 . . . N; (e) a Log-MAP module computing the softdecision output based on the branch metric values and state metricvalues using log maximum a posteriori probability algorithm; (f) aControl Logic state machine module controlling the overall operations ofthe Log-MAP decoder.
 10. The Decoder system of claim c7, wherein thedecoder uses the logarithm maximum a posteriori probability algorithm.11. The Decoder system of claim c7, wherein the decoder uses thesoft-input and soft-output (SISO) logarithm maximum a posterioriprobability algorithm.
 12. The Decoder system of claim c7, wherein thedecoder uses a convolutional 8-states trellis state transition diagram.13. The Decoder system of claim c7, wherein the the branch metric moduleuses a binary adder, a binary Subtracter, and two binarytwo-complementers logic.
 14. The Decoder system of claim c7, wherein thethe state metric module uses a binary adder, a comparator, a Muxselector logic.
 15. The Decoder system of claim c7, wherein the thelog-map module uses binary adders, binary maximum selectors logic. 16.The Decoder system of claim c7, wherein the soft decoder module usessoft decision algorithm.
 17. The Decoder system of claim c7, wherein thethe branch metric memory module uses dual-port memory RAM.